Testing and Timing DDR3 and DDR4

DDR SDRAM (double data rate synchronous dynamic random-access memory) design is very challenging in embedded single board computer design (SBC). This is especially true when it comes to PCB layout. The DDR section of the PCB layout can be one of the most time consuming areas within the PCB design. In small form factor, embedded SBC design it can also be one of the most dense areas of the PCB. Real estate is typically at a premium which means adding hardware “hooks” for debugging a DDR interface may not be practical or even possible. PCB layout is one of the key elements that affect whether a DDR design is successful or not. Following DDR manufacturer’s guidelines and recommendations for PCB layout and design is essential. Performing pre-layout simulations helps to guide PCB layout, and adhering to good PCB layout design practices is a must. DDR memory design is not for the “faint of heart”.
After everything has been done to insure a good SBC design, it’s time to see if all of those efforts have paid off. I have done many board bring-ups for boards designed by Embedded Planet. These board designs have had SDR SDRAM (single data rate), DDR1, DDR2, DDR3, and soon DDR4 interfaces. Many processor manufacturers provide SDKs for their processors based on open source u-boot and Linux. Embedded Planet boards typically use u-boot for board initialization and boot code to take advantage of the work done by processor manufacturers and by many other seasoned developers. For most Embedded Planet boards u-boot resides in NOR FLASH.
After DDR controller initialization u-boot relocates itself to RAM memory. U-boot running in RAM is a good first step in DDR testing. U-boot provides a memory test (mtest) that can be run to verify correct DDR configuration but be aware that this memory test is not robust enough to expose some DDR timing errors that can cause intermittent faults and non-deterministic faults. Don’t rule out DDR controller and timing problems if you run into difficulties getting an OS up and running or if you experience intermittent faults even if the DDR memory passes the mtest run in u-boot. A utility called memtester for Linux is a user-space utility for testing memory and is good for exposing intermittent and non-deterministic faults.
Many DDR controller parameters can be configured based on timing parameters that come directly from the manufacturer’s data sheet when using discrete DDR memory components and from the SPD EEPROM of a DIMM module. Usually a few DDR controller parameters, however, are board and PCB layout specific such as the CPO and CLK_ADJUST parameters in the DDR controllers of Freescale’s PowerQUICC and QorIQ processors. A good place to start trying to resolve any DDR faults is by identifying and then paying special attention to these board specific parameters.