“Poke and Hope” Programming – Blog Entry by Greg Davis

The data sheets or reference manuals for 64-bit and 32-bit system-on-chip (SOC) processors have hundreds and even thousands of pages.  For example Embedded Planet has board designs based on Freescale QorIQ processors and Cavium OCTEON processors.  The hardware reference manual for the Freescale P5020 QorIQ Integrated Multicore Communication processor is 1997 pages.  The hardware reference manual for the Cavium OCTEON II CN66XX processor is 1868 pages.  This is a lot of information to work through. Especially for software engineers tasked with getting the various processor interfaces that are supported in a board design up and running and fully tested.

The technical writers that work for the processor vendors have a daunting task when it comes to documenting these complicated processors.  In many cases, the descriptions provided in a data sheet for individual programming bits can be very cryptic and lacking in sufficient detail.  Working with field application engineers (FAE) or tech support personnel to extract the exact meaning, determine the specific sequence, glean the intended operation, or to just connect the dots can be very time consuming.  Often times to combat this many programmers fall into a programming technique I like to call “poke and hope” programming.  This is not meant to be a negative moniker or a disparaging tag line given to this programming approach.  Rather this commentary is intended to highlight this approach as being an effective method to quickly answer questions about the intended meaning behind an unclear description.  The key word here being “quickly”.

Usually the “poke and hope” method involves creating a simple loop that sets then tests a valid register value or combination of register values.  On each iteration of the loop there needs to be test that is sufficient enough to verify proper operation.  On positive verification or result the test can exit the loop.

Don’t misunderstand these comments; it is always best to fully understand the operation of an interface and its related settings.  Usually the good intention of project managers is to allow sufficient time in a project schedule to fully understand any new processor features and interfaces.  Reality is that this “extra” time is often consumed by other project issues or by other unforeseen and unaccounted for tasks.  Bottom line is that any method employed to get to completion will be appreciated by management.

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